Latest news

  • Featured Image 2017 Call for Eastern Partnership Participation

    Enlighten Your Research launches 2017 call for Eastern Partnership participation The 2017 Call for Participation is open for Eastern Partnership research collaborations to submit Enlighten Your Research proposals. The deadline is midnight CET on Friday 7 April 2017. For more information about this call and how to submit a proposal, and to be inspired by […]

  • Featured Image IXPUG Annual Spring Conference 2017

    Call for Presentations Intel Xeon Phi User Group (IXPUG) Annual Spring Conference 2011 The Stephen Hawking Centre for Theoretical Cosmology, Univerity of Cambridge, UK 11th – 13th April 2017 Abstract Submission Deadline: Sun 26th February IXPUG is about sharing ideas, implementations, and experiences that will help users take advantage of the latest in Intel […]

  • CSCS HPC Summer School 2017

    ETHZ-CSCS and USI organize a 2-week Summer School from July 16 through July 28, 2015, in Serpiano, Tessin. The hotel is positioned on Mount San Giorgio, UNESCO World Heritage site since 2003. The Summer School will focus on the effective exploitation of High Performance Computing (HPC) systems. More details can be found on our webpage […]

  • Featured Image CERIC Call for Proposals

    CERIC-ERIC is launching its seventh call for proposals, with a two-steps deadline option: March1st, to have a pre-evaluation and improve your proposals according to the feedback received; March 30th, recommended only for expert users of all the techniques requested. In this call, there are 47 instruments available, as well as the opportunity of getting awards […]

  • GASPI – Global Address Space Programming Interface

    In this tutorial we present an asynchronous data flow programming model for Partitioned Global Address Spaces (PGAS) as an alternative to the programming model of MPI. GASPI, which stands for Global Address Space Programming Interface, is a partitioned global address space API. The GASPI API is designed as a C/C++/Fortran library and focused on three […]

  • Featured Image PRACE opens Tier-1 for Tier-0 service

    PRACE Preparatory Access is an established rolling Call for Proposals which supports researchers in Europe to port and adapt their applications to the PRACE Tier-0 infrastructure. The objective of PRACE Preparatory Access is to allow PRACE users to optimise, scale and test codes on PRACE systems, to prepare for Project Access. This new Preparatory Access (PA) Type D offers users to start the optimisation work on a PRACE Tier-1 national system to finally reach PRACE Tier-0 system scalability.

  • Best Practice Guide – Intel Xeon Phi, January 2017

    Best Practice Guide Intel Xeon Phi v2.0 Emanouil Atanassov IICT-BAS, Bulgaria Michaela Barth KTH, Sweden Mikko Byckling CSC, Finland Vali Codreanu SURFsara, Netherlands Nevena Ilieva NCSA, Bulgaria Tomas Karasek IT4Innovations, Czech Republic Jorge Rodriguez BSC, Spain Sami Saarinen CSC, Finland Ole Widar Saastad University of Oslo, Norway Michael Schliephake KTH, Sweden Martin Stachon IT4Innovations, Czech […]

  • Best Practice Guide – Haswell/Broadwell, January 2017

    Best Practice Guide Haswell/Broadwell Vali Codreanu SURFsara Joerg Hertzer HLRS Cristian Morales BSC Jorge Rodriguez BSC Ole Widar Saastad University of Oslo Martin Stachon IT4Innovations Volker Weinberg (Editor) LRZ 31-01-2017 Table of Contents 1. Introduction 2. System Architecture 2.1. Overview System Architecture 2.2. Processor Architecture 2.2.1. Instruction set 2.3. Memory Architecture 3. Programming Environment / […]