• PRACE Training Centres (PTCs)

  • PRACE operates ten PRACE Training Centres (PTCs) and they have established a state-of-the-art curriculum for training in HPC and scientific computing. PTCs carry out and coordinate training and education activities that enable both European academic researchers and European industry to utilise the computational infrastructure available through PRACE and provide top-class education and training opportunities for computational scientists in Europe.
    With approximately 100 training events each year, the ten PRACE Training Centres (PTCs) are based at:

    PTC training events are advertised on the following pages. Registration is free and open to all (pending availability):
    https://events.prace-ri.eu/category/2/

    The following figure depicts the location of the PTC centers throughout Europe.
    PATC, PTC location

    PATC events this month:

    April 2019
    Mon Tue Wed Thu Fri Sat Sun
    GPU-accelerated computing drives current scientific research. Writing fast numeric algorithms for GPUs offers high application performance by offloading compute-intensive portions of the code to an NVIDIA GPU. The course will cover basic aspects of GPU architectures and programming. Focus is on the usage of the parallel programming language CUDA-C which allows maximum control of NVIDIA GPU hardware. Examples of increasing complexity will be used to demonstrate optimization and tuning of scientific applications.

    Topics covered will include:


    Introduction to GPU/Parallel computing
    Programming model CUDA
    GPU libraries like CuBLAS and CuFFT
    Tools for debugging and profiling
    Performance optimizations


    Prerequisites: Some knowledge about Linux, e.g. make, command line editor, Linux shell, experience in C/C++

    Application
    Registrations are only considered until 28 February 2018 due to available space, the maximal number of participants is limited. Applicants will be notified, whether they are accepted for participitation.

    Instructors: Dr. Jan Meinke, Jochen Kreutz, Dr. Andreas Herten, JSC; Jiri Kraus, NVIDIA

    Contact
    For any questions concerning the course please send an e-mail to j.meinke@fz-juelich.de
    events.prace-ri.eu/event/823/
    Apr 1 9:00 to Apr 3 16:30
    This course gives an overview of the most relevant GPGPU computing techniques to accelerate computationally demanding tasks on HPC heterogeneous architectures based on GPUs.

    The course will start with an architectural overview of modern GPU based heterogeneous architectures, focusing on its computing power versus data movement needs. The course will cover both a high level (pragma-based) programming approach with OpenACC for a fast porting startup, and lower level approaches based on nVIDIA CUDA and OpenCL programming languages for finer grained computational intensive tasks. A particular attention will be given on performance tuning and techniques to overcome common data movement bottlenecks and patterns.

    Topics:

    Overview of architectural trends of GPUs in HPC. GPGPU parallel programming in heterogeneous architectures. Basis of OpenACC, CUDA and OpenCL programming.

    Skills:
    By the end of the course, students will be able to:


    understand the strengths and weaknesses of GPUs as accelerators
    program GPU accelerated applications using both higher and lower level programming approaches
    overcome problems and bottlenecks regarding data movement between host and device memories
    make best use of independent execution queues for concurrent computing/data-movement operations


    Target Audience:
    Researchers and programmers interested in porting scientific applications or use efficient post-process and data-analysis techniques in modern heterogeneous HPC architectures.

    Prerequisites:

    A basic knowledge of C or Fortran is mandatory. Programming and Linux or Unix. A basic knowledge of any parallel programming technique/paradigm is recommended.

    Grant:
    The lunch for the three days will be offered to all the participants and some grants are available. The only requirement to be eligible is to be not funded by your institution to attend the course and to work or live in an institute outside the Roma area. The grant  will be 300 euros for students working and living outside Italy and 150 euros for students working and living in Italy (outside Roma). Some documentation will be required and the grant will be paid only after a certified presence of minimum 80% of the lectures.

    Further information about how to request the grant, will be provided at the confirmation of the course: about 3 weeks before the starting date.

    Coordinating Teacher: Dr. L.Ferraro

     
    events.prace-ri.eu/event/830/
    Apr 1 9:00 to Apr 3 18:00
    When developing a numerical simulation code with high performance and efficiency in mind, one is often compelled to accept a trade-off between using a native-hardware programming model (like CUDA or OpenCL), which has become tremendously challenging, and loosing some cross-platform portability.

    Porting a large existing legacy code to a modern HPC platform, and developing a new simulation code, are two different tasks that may be benefit from a high-level programming model, which abstracts the low-level hardware details.

    This training presents existing high-level programming solutions that can preserve at best as possible performance, maintainability and portability across the vast diversity of modern hardware architectures (multicore CPU, manycore, GPU, ARM, ..) and software development productivity.

    We will  provide an introduction to the high-level C++ programming model Kokkos github.com/kokkos, and show basic code examples  to illustrate the following concepts through hands-on sessions:


    hardware portability: design an algorithm once and let the Kokkos back-end (OpenMP, CUDA, ...) actually derive an efficient low-level implementation;
    efficient architecture-aware memory containers: what is a Kokkos::view;
    revisit fundamental parallel patterns with Kokkos: parallel for, reduce, scan, ... ;
    explore some mini-applications.


    Several detailed examples in C/C++/Fortran will be used in hands-on session on the high-end hardware platform Ouessant (www.idris.fr/ouessant/), equipped with Nvidia Pascal GPUs.

    Prerequisites:
    Some basic knowledge of the CUDA programming model and of C++.
    events.prace-ri.eu/event/818/
    Apr 1 9:30 to Apr 2 17:00
    GPU-accelerated computing drives current scientific research. Writing fast numeric algorithms for GPUs offers high application performance by offloading compute-intensive portions of the code to an NVIDIA GPU. The course will cover basic aspects of GPU architectures and programming. Focus is on the usage of the parallel programming language CUDA-C which allows maximum control of NVIDIA GPU hardware. Examples of increasing complexity will be used to demonstrate optimization and tuning of scientific applications.

    Topics covered will include:


    Introduction to GPU/Parallel computing
    Programming model CUDA
    GPU libraries like CuBLAS and CuFFT
    Tools for debugging and profiling
    Performance optimizations


    Prerequisites: Some knowledge about Linux, e.g. make, command line editor, Linux shell, experience in C/C++

    Application
    Registrations are only considered until 28 February 2018 due to available space, the maximal number of participants is limited. Applicants will be notified, whether they are accepted for participitation.

    Instructors: Dr. Jan Meinke, Jochen Kreutz, Dr. Andreas Herten, JSC; Jiri Kraus, NVIDIA

    Contact
    For any questions concerning the course please send an e-mail to j.meinke@fz-juelich.de
    events.prace-ri.eu/event/823/
    Apr 1 9:00 to Apr 3 16:30
    When developing a numerical simulation code with high performance and efficiency in mind, one is often compelled to accept a trade-off between using a native-hardware programming model (like CUDA or OpenCL), which has become tremendously challenging, and loosing some cross-platform portability.

    Porting a large existing legacy code to a modern HPC platform, and developing a new simulation code, are two different tasks that may be benefit from a high-level programming model, which abstracts the low-level hardware details.

    This training presents existing high-level programming solutions that can preserve at best as possible performance, maintainability and portability across the vast diversity of modern hardware architectures (multicore CPU, manycore, GPU, ARM, ..) and software development productivity.

    We will  provide an introduction to the high-level C++ programming model Kokkos github.com/kokkos, and show basic code examples  to illustrate the following concepts through hands-on sessions:


    hardware portability: design an algorithm once and let the Kokkos back-end (OpenMP, CUDA, ...) actually derive an efficient low-level implementation;
    efficient architecture-aware memory containers: what is a Kokkos::view;
    revisit fundamental parallel patterns with Kokkos: parallel for, reduce, scan, ... ;
    explore some mini-applications.


    Several detailed examples in C/C++/Fortran will be used in hands-on session on the high-end hardware platform Ouessant (www.idris.fr/ouessant/), equipped with Nvidia Pascal GPUs.

    Prerequisites:
    Some basic knowledge of the CUDA programming model and of C++.
    events.prace-ri.eu/event/818/
    Apr 1 9:30 to Apr 2 17:00
    This course gives an overview of the most relevant GPGPU computing techniques to accelerate computationally demanding tasks on HPC heterogeneous architectures based on GPUs.

    The course will start with an architectural overview of modern GPU based heterogeneous architectures, focusing on its computing power versus data movement needs. The course will cover both a high level (pragma-based) programming approach with OpenACC for a fast porting startup, and lower level approaches based on nVIDIA CUDA and OpenCL programming languages for finer grained computational intensive tasks. A particular attention will be given on performance tuning and techniques to overcome common data movement bottlenecks and patterns.

    Topics:

    Overview of architectural trends of GPUs in HPC. GPGPU parallel programming in heterogeneous architectures. Basis of OpenACC, CUDA and OpenCL programming.

    Skills:
    By the end of the course, students will be able to:


    understand the strengths and weaknesses of GPUs as accelerators
    program GPU accelerated applications using both higher and lower level programming approaches
    overcome problems and bottlenecks regarding data movement between host and device memories
    make best use of independent execution queues for concurrent computing/data-movement operations


    Target Audience:
    Researchers and programmers interested in porting scientific applications or use efficient post-process and data-analysis techniques in modern heterogeneous HPC architectures.

    Prerequisites:

    A basic knowledge of C or Fortran is mandatory. Programming and Linux or Unix. A basic knowledge of any parallel programming technique/paradigm is recommended.

    Grant:
    The lunch for the three days will be offered to all the participants and some grants are available. The only requirement to be eligible is to be not funded by your institution to attend the course and to work or live in an institute outside the Roma area. The grant  will be 300 euros for students working and living outside Italy and 150 euros for students working and living in Italy (outside Roma). Some documentation will be required and the grant will be paid only after a certified presence of minimum 80% of the lectures.

    Further information about how to request the grant, will be provided at the confirmation of the course: about 3 weeks before the starting date.

    Coordinating Teacher: Dr. L.Ferraro

     
    events.prace-ri.eu/event/830/
    Apr 1 9:00 to Apr 3 18:00
    GPU-accelerated computing drives current scientific research. Writing fast numeric algorithms for GPUs offers high application performance by offloading compute-intensive portions of the code to an NVIDIA GPU. The course will cover basic aspects of GPU architectures and programming. Focus is on the usage of the parallel programming language CUDA-C which allows maximum control of NVIDIA GPU hardware. Examples of increasing complexity will be used to demonstrate optimization and tuning of scientific applications.

    Topics covered will include:


    Introduction to GPU/Parallel computing
    Programming model CUDA
    GPU libraries like CuBLAS and CuFFT
    Tools for debugging and profiling
    Performance optimizations


    Prerequisites: Some knowledge about Linux, e.g. make, command line editor, Linux shell, experience in C/C++

    Application
    Registrations are only considered until 28 February 2018 due to available space, the maximal number of participants is limited. Applicants will be notified, whether they are accepted for participitation.

    Instructors: Dr. Jan Meinke, Jochen Kreutz, Dr. Andreas Herten, JSC; Jiri Kraus, NVIDIA

    Contact
    For any questions concerning the course please send an e-mail to j.meinke@fz-juelich.de
    events.prace-ri.eu/event/823/
    Apr 1 9:00 to Apr 3 16:30
    This course gives an overview of the most relevant GPGPU computing techniques to accelerate computationally demanding tasks on HPC heterogeneous architectures based on GPUs.

    The course will start with an architectural overview of modern GPU based heterogeneous architectures, focusing on its computing power versus data movement needs. The course will cover both a high level (pragma-based) programming approach with OpenACC for a fast porting startup, and lower level approaches based on nVIDIA CUDA and OpenCL programming languages for finer grained computational intensive tasks. A particular attention will be given on performance tuning and techniques to overcome common data movement bottlenecks and patterns.

    Topics:

    Overview of architectural trends of GPUs in HPC. GPGPU parallel programming in heterogeneous architectures. Basis of OpenACC, CUDA and OpenCL programming.

    Skills:
    By the end of the course, students will be able to:


    understand the strengths and weaknesses of GPUs as accelerators
    program GPU accelerated applications using both higher and lower level programming approaches
    overcome problems and bottlenecks regarding data movement between host and device memories
    make best use of independent execution queues for concurrent computing/data-movement operations


    Target Audience:
    Researchers and programmers interested in porting scientific applications or use efficient post-process and data-analysis techniques in modern heterogeneous HPC architectures.

    Prerequisites:

    A basic knowledge of C or Fortran is mandatory. Programming and Linux or Unix. A basic knowledge of any parallel programming technique/paradigm is recommended.

    Grant:
    The lunch for the three days will be offered to all the participants and some grants are available. The only requirement to be eligible is to be not funded by your institution to attend the course and to work or live in an institute outside the Roma area. The grant  will be 300 euros for students working and living outside Italy and 150 euros for students working and living in Italy (outside Roma). Some documentation will be required and the grant will be paid only after a certified presence of minimum 80% of the lectures.

    Further information about how to request the grant, will be provided at the confirmation of the course: about 3 weeks before the starting date.

    Coordinating Teacher: Dr. L.Ferraro

     
    events.prace-ri.eu/event/830/
    Apr 1 9:00 to Apr 3 18:00
    The registration to this course is now open.

    All PATC Courses at BSC do not charge fees.

    PLEASE BRING YOUR OWN LAPTOP.

    Local Web Page:
    This is an expansion of the topic "OpenACC and other approaches to GPU computing" covered on this year's and last year's editions of the Introduction to CUDA Programming.
    This course will provide very good introduction to the PUMPS Summer School run jointly with NVIDIA -  also  at Campus Nord, Barcelona. For further information visit the school website.

    Convener: Antonio Peña, Computer Sciences Senior Researcher, Accelerators and Communications for High Performance Computing, BSC


    Objectives: 

    As an NVIDIA GPU Center of Excellence, BSC and UPC are deeply involved in research and outreach activities around GPU Computing. OpenACC is a high-level, directive-based programming model for GPU computing. It is a very convenient language to leverage the GPU power with minimal code modifications, being the preferred option for non computer scientists. This course will cover the necessary topics to get started with GPU programming in OpenACC, as well as some advanced topics.

    The target audiences of the course are students who want to develop exciting applications for these processors, as well as those who want to develop programming tools and future implementations for these processors.

    Level: 
    BEGINNERS: for trainees from different background or very little knowledge.

    Agenda:

    DAY 1

    Session 1 / 9:00am – 1:00 pm (2h lectures, 2 h practical)

    9:00 - 10:00 Introduction to OpenACC on x86 CPU and GPU

    10:00 - 11:00 Hands-on: Introduction

    11:00 - 11:30 Break

    11:30 - 12:30 Profiling and Parallelizing with the OpenACC Toolkit

    12:30 - 13:30 Hands-on: Profiling and Parallelizing

    13:30 - 15:00 Lunch break

    Session 2 / 2:00pm – 5:00 pm (2 h practical)

    15:00 - 17:00 Hands-on: Open Labs

     

    DAY 2

    Session 3 / 9:00am – 1:00 pm (2h lectures, 2 h practical)

    9:00 - 10:00 Expressing Data Locality and Optimizations with OpenACC

    10:00 - 11:00 Hands-on: Data Locality and Optimizations

    11:00 - 11:30 Break

    11:30 - 12:30 Advanced OpenACC Techniques: Interoperability, MPI, and Pipelining

    12:30 - 13:30 Hands-on: Advanced Techniques

    13:30 - 15:00 Lunch break

    Session 4 / 2:00pm – 5:00 pm (2 h practical)

    15:00 - 17:00 Hands-on: Open Labs

    End of Course

     
    events.prace-ri.eu/event/769/
    Apr 4 9:00 to Apr 5 18:00
    The registration to this course is now open.

    All PATC Courses at BSC do not charge fees.

    PLEASE BRING YOUR OWN LAPTOP.

    Local Web Page:
    This is an expansion of the topic "OpenACC and other approaches to GPU computing" covered on this year's and last year's editions of the Introduction to CUDA Programming.
    This course will provide very good introduction to the PUMPS Summer School run jointly with NVIDIA -  also  at Campus Nord, Barcelona. For further information visit the school website.

    Convener: Antonio Peña, Computer Sciences Senior Researcher, Accelerators and Communications for High Performance Computing, BSC


    Objectives: 

    As an NVIDIA GPU Center of Excellence, BSC and UPC are deeply involved in research and outreach activities around GPU Computing. OpenACC is a high-level, directive-based programming model for GPU computing. It is a very convenient language to leverage the GPU power with minimal code modifications, being the preferred option for non computer scientists. This course will cover the necessary topics to get started with GPU programming in OpenACC, as well as some advanced topics.

    The target audiences of the course are students who want to develop exciting applications for these processors, as well as those who want to develop programming tools and future implementations for these processors.

    Level: 
    BEGINNERS: for trainees from different background or very little knowledge.

    Agenda:

    DAY 1

    Session 1 / 9:00am – 1:00 pm (2h lectures, 2 h practical)

    9:00 - 10:00 Introduction to OpenACC on x86 CPU and GPU

    10:00 - 11:00 Hands-on: Introduction

    11:00 - 11:30 Break

    11:30 - 12:30 Profiling and Parallelizing with the OpenACC Toolkit

    12:30 - 13:30 Hands-on: Profiling and Parallelizing

    13:30 - 15:00 Lunch break

    Session 2 / 2:00pm – 5:00 pm (2 h practical)

    15:00 - 17:00 Hands-on: Open Labs

     

    DAY 2

    Session 3 / 9:00am – 1:00 pm (2h lectures, 2 h practical)

    9:00 - 10:00 Expressing Data Locality and Optimizations with OpenACC

    10:00 - 11:00 Hands-on: Data Locality and Optimizations

    11:00 - 11:30 Break

    11:30 - 12:30 Advanced OpenACC Techniques: Interoperability, MPI, and Pipelining

    12:30 - 13:30 Hands-on: Advanced Techniques

    13:30 - 15:00 Lunch break

    Session 4 / 2:00pm – 5:00 pm (2 h practical)

    15:00 - 17:00 Hands-on: Open Labs

    End of Course

     
    events.prace-ri.eu/event/769/
    Apr 4 9:00 to Apr 5 18:00
    6
     
    7
     
    The registration to this course is now open.

    All PATC Courses at BSC do not charge fees.

    PLEASE BRING YOUR OWN LAPTOP.

    Local Web Page: This course will provide very good introduction to the PUMPS Summer School run jointly with NVIDIA -also  at Campus Nord, Barcelona. For further information visit the school website  as this school has attendee selection process.
    You may also be interested in our Introduction to OpenACC course.

    Convener: 
    Antonio Peña, Computer Sciences Senior Researcher, Accelerators and Communications for High Performance Computing, BSC

    Objectives: 

    The aim of this course is to provide students with knowledge and hands-on experience in developing applications software for processors with massively parallel computing resources. In general, we refer to a processor as massively parallel if it has the ability to complete more than 64 arithmetic operations per clock cycle. Many commercial offerings from NVIDIA, AMD, and Intel already offer such levels of concurrency. Effectively programming these processors will require in-depth knowledge about parallel programming principles, as well as the parallelism models, communication models, and resource limitations of these processors.

    Agenda:

    DAY 1

    Session 1 / 9:00am – 1:00 pm (3:30 h lectures)

    L1 9:00-10:45 The GPU hardware: Many-core Nvidia developments

    10:45-11:15 Coffee break

    L2 11:15-13:00 CUDA Programming: Threads, blocks, kernels, grids

    13:00-14:00 Lunch break

     

    Session 2 / 2:00pm – 6:00 pm (3:30 h lectures)

    L3 14:00-15:45 CUDA Tools: Compiling, debugging, profiling, occupancy calculator

    15:45-16:15 Coffee break

    L4 16:15-18:00 CUDA Examples(1): VectorAdd, Stencil, ReverseArray

     

    DAY 2

    Session 3 / 9:00am – 1:00 pm (3:30 h lectures)

    L5   9:00-10:45 CUDA Examples (2): Matrices Multiply. Assorted optimizations

    10:45-11:15 Coffee break

    L6 11:15-13:00 CUDA Examples (3): Dynamic parallelism, Hyper-Q, unified memory

    13:00-14:00 Lunch break

     

    Session 4 / 2:00pm – 6:00 pm (3:30 h practical)

    H1 14:00-15:45 Hands-on Lab 1

    15:45-16:15 Coffee break

    H2 16:15-18:00 Hands-on Lab 2

     

    DAY 3

    Session 5 / 9:00am – 1:00 pm (3:30 h lectures)

    L7 9:00-10:45 Inside Pascal: Multiprocessors, stacked memory, NV-link

    10:45-11:15 Coffee break

    L8 11:15-13:00 OpenACC and other approaches to GPU computing

    13:00-14:00 Lunch break

     

    Session 6 / 2:00pm – 6:00 pm (3:30 h practical)

    H3 14:00-15:45 Hands-on Lab 3

    15:45-16:15 Coffee break

    H4 16:15-18:00 Hands-on Lab 4

     

    DAY 4

    Session 7 / 9:00am – 1:00 pm (3:30 h practical)

    H5 9:00-10:45 Hands-on Lab 5

    10:45-11:15 Coffee break

    H6 11:15-13:00 Hands-on Lab 6

    13:00-14:00 Lunch break

     

    Session 8 / 2:00pm – 6:00 pm (3:30 h practical)

    H7 14:00-15:45 Hands-on Lab 7

     15:45-16:15 Coffee break

    H8 16:15-18:00 Free Hands-on Lab

    End of Course

    The target audiences of the course are students who want to develop exciting applications for these processors, as well as those who want to develop programming tools and future implementations for these processors.

    Level: INTERMEDIATE: for trainees with some theoretical and practical knowledge; those who finished the beginners course

    ADVANCED: for trainees able to work independently and requiring guidance for solving complex problems

    Prerequisites: Basics of C programming and concepts of parallel processing will help, but are not critical to follow the lectures.
    events.prace-ri.eu/event/768/
    Apr 8 9:00 to Apr 11 18:00
    The registration to this course is now open.

    All PATC Courses at BSC do not charge fees.

    PLEASE BRING YOUR OWN LAPTOP.

    Local Web Page: This course will provide very good introduction to the PUMPS Summer School run jointly with NVIDIA -also  at Campus Nord, Barcelona. For further information visit the school website  as this school has attendee selection process.
    You may also be interested in our Introduction to OpenACC course.

    Convener: 
    Antonio Peña, Computer Sciences Senior Researcher, Accelerators and Communications for High Performance Computing, BSC

    Objectives: 

    The aim of this course is to provide students with knowledge and hands-on experience in developing applications software for processors with massively parallel computing resources. In general, we refer to a processor as massively parallel if it has the ability to complete more than 64 arithmetic operations per clock cycle. Many commercial offerings from NVIDIA, AMD, and Intel already offer such levels of concurrency. Effectively programming these processors will require in-depth knowledge about parallel programming principles, as well as the parallelism models, communication models, and resource limitations of these processors.

    Agenda:

    DAY 1

    Session 1 / 9:00am – 1:00 pm (3:30 h lectures)

    L1 9:00-10:45 The GPU hardware: Many-core Nvidia developments

    10:45-11:15 Coffee break

    L2 11:15-13:00 CUDA Programming: Threads, blocks, kernels, grids

    13:00-14:00 Lunch break

     

    Session 2 / 2:00pm – 6:00 pm (3:30 h lectures)

    L3 14:00-15:45 CUDA Tools: Compiling, debugging, profiling, occupancy calculator

    15:45-16:15 Coffee break

    L4 16:15-18:00 CUDA Examples(1): VectorAdd, Stencil, ReverseArray

     

    DAY 2

    Session 3 / 9:00am – 1:00 pm (3:30 h lectures)

    L5   9:00-10:45 CUDA Examples (2): Matrices Multiply. Assorted optimizations

    10:45-11:15 Coffee break

    L6 11:15-13:00 CUDA Examples (3): Dynamic parallelism, Hyper-Q, unified memory

    13:00-14:00 Lunch break

     

    Session 4 / 2:00pm – 6:00 pm (3:30 h practical)

    H1 14:00-15:45 Hands-on Lab 1

    15:45-16:15 Coffee break

    H2 16:15-18:00 Hands-on Lab 2

     

    DAY 3

    Session 5 / 9:00am – 1:00 pm (3:30 h lectures)

    L7 9:00-10:45 Inside Pascal: Multiprocessors, stacked memory, NV-link

    10:45-11:15 Coffee break

    L8 11:15-13:00 OpenACC and other approaches to GPU computing

    13:00-14:00 Lunch break

     

    Session 6 / 2:00pm – 6:00 pm (3:30 h practical)

    H3 14:00-15:45 Hands-on Lab 3

    15:45-16:15 Coffee break

    H4 16:15-18:00 Hands-on Lab 4

     

    DAY 4

    Session 7 / 9:00am – 1:00 pm (3:30 h practical)

    H5 9:00-10:45 Hands-on Lab 5

    10:45-11:15 Coffee break

    H6 11:15-13:00 Hands-on Lab 6

    13:00-14:00 Lunch break

     

    Session 8 / 2:00pm – 6:00 pm (3:30 h practical)

    H7 14:00-15:45 Hands-on Lab 7

     15:45-16:15 Coffee break

    H8 16:15-18:00 Free Hands-on Lab

    End of Course

    The target audiences of the course are students who want to develop exciting applications for these processors, as well as those who want to develop programming tools and future implementations for these processors.

    Level: INTERMEDIATE: for trainees with some theoretical and practical knowledge; those who finished the beginners course

    ADVANCED: for trainees able to work independently and requiring guidance for solving complex problems

    Prerequisites: Basics of C programming and concepts of parallel processing will help, but are not critical to follow the lectures.
    events.prace-ri.eu/event/768/
    Apr 8 9:00 to Apr 11 18:00
    Interactive exploration and analysis of large amounts of data from scientific simulations, in-situ visualization and application control are convincing scenarios for explorative sciences. Based on the open source software Jupyter or JupyterLab, a way has been available for some time now that combines interactive with reproducible computing while at the same time meeting the challenges of support for the wide range of different software workflows.

    Even on supercomputers, the method enables the creation of documents that combine live code with narrative text, mathematical equations, visualizations, interactive controls, and other extensive output. However, a number of challenges must be mastered in order to make existing workflows ready for interactive high-performance computing. With so many possibilities, it's easy to lose sight of the big picture. This course provides a detailed introduction to interactive high-performance computing.

    The following topics are covered:


    Opportunities and challenges of interactive HPC
    Functionality and interaction of the necessary components
    Introduction to the most important libraries
    Coupling and control of simulations
    Visualizing results interactively


     

    Prerequisites: Experience in Python

    Application
    Registrations are only considered until 15 March 2018 due to available space, the maximal number of participants is limited. Applicants will be notified, whether they are accepted for participitation.

    Instructors: Jens Henrik Göbbert, Alice Grosch, JSC

    Contact
    For any questions concerning the course please send an e-mail to j.goebbert@fz-juelich.de
    events.prace-ri.eu/event/826/
    Apr 9 9:00 to Apr 10 16:30
    The registration to this course is now open.

    All PATC Courses at BSC do not charge fees.

    PLEASE BRING YOUR OWN LAPTOP.

    Local Web Page: This course will provide very good introduction to the PUMPS Summer School run jointly with NVIDIA -also  at Campus Nord, Barcelona. For further information visit the school website  as this school has attendee selection process.
    You may also be interested in our Introduction to OpenACC course.

    Convener: 
    Antonio Peña, Computer Sciences Senior Researcher, Accelerators and Communications for High Performance Computing, BSC

    Objectives: 

    The aim of this course is to provide students with knowledge and hands-on experience in developing applications software for processors with massively parallel computing resources. In general, we refer to a processor as massively parallel if it has the ability to complete more than 64 arithmetic operations per clock cycle. Many commercial offerings from NVIDIA, AMD, and Intel already offer such levels of concurrency. Effectively programming these processors will require in-depth knowledge about parallel programming principles, as well as the parallelism models, communication models, and resource limitations of these processors.

    Agenda:

    DAY 1

    Session 1 / 9:00am – 1:00 pm (3:30 h lectures)

    L1 9:00-10:45 The GPU hardware: Many-core Nvidia developments

    10:45-11:15 Coffee break

    L2 11:15-13:00 CUDA Programming: Threads, blocks, kernels, grids

    13:00-14:00 Lunch break

     

    Session 2 / 2:00pm – 6:00 pm (3:30 h lectures)

    L3 14:00-15:45 CUDA Tools: Compiling, debugging, profiling, occupancy calculator

    15:45-16:15 Coffee break

    L4 16:15-18:00 CUDA Examples(1): VectorAdd, Stencil, ReverseArray

     

    DAY 2

    Session 3 / 9:00am – 1:00 pm (3:30 h lectures)

    L5   9:00-10:45 CUDA Examples (2): Matrices Multiply. Assorted optimizations

    10:45-11:15 Coffee break

    L6 11:15-13:00 CUDA Examples (3): Dynamic parallelism, Hyper-Q, unified memory

    13:00-14:00 Lunch break

     

    Session 4 / 2:00pm – 6:00 pm (3:30 h practical)

    H1 14:00-15:45 Hands-on Lab 1

    15:45-16:15 Coffee break

    H2 16:15-18:00 Hands-on Lab 2

     

    DAY 3

    Session 5 / 9:00am – 1:00 pm (3:30 h lectures)

    L7 9:00-10:45 Inside Pascal: Multiprocessors, stacked memory, NV-link

    10:45-11:15 Coffee break

    L8 11:15-13:00 OpenACC and other approaches to GPU computing

    13:00-14:00 Lunch break

     

    Session 6 / 2:00pm – 6:00 pm (3:30 h practical)

    H3 14:00-15:45 Hands-on Lab 3

    15:45-16:15 Coffee break

    H4 16:15-18:00 Hands-on Lab 4

     

    DAY 4

    Session 7 / 9:00am – 1:00 pm (3:30 h practical)

    H5 9:00-10:45 Hands-on Lab 5

    10:45-11:15 Coffee break

    H6 11:15-13:00 Hands-on Lab 6

    13:00-14:00 Lunch break

     

    Session 8 / 2:00pm – 6:00 pm (3:30 h practical)

    H7 14:00-15:45 Hands-on Lab 7

     15:45-16:15 Coffee break

    H8 16:15-18:00 Free Hands-on Lab

    End of Course

    The target audiences of the course are students who want to develop exciting applications for these processors, as well as those who want to develop programming tools and future implementations for these processors.

    Level: INTERMEDIATE: for trainees with some theoretical and practical knowledge; those who finished the beginners course

    ADVANCED: for trainees able to work independently and requiring guidance for solving complex problems

    Prerequisites: Basics of C programming and concepts of parallel processing will help, but are not critical to follow the lectures.
    events.prace-ri.eu/event/768/
    Apr 8 9:00 to Apr 11 18:00
    Interactive exploration and analysis of large amounts of data from scientific simulations, in-situ visualization and application control are convincing scenarios for explorative sciences. Based on the open source software Jupyter or JupyterLab, a way has been available for some time now that combines interactive with reproducible computing while at the same time meeting the challenges of support for the wide range of different software workflows.

    Even on supercomputers, the method enables the creation of documents that combine live code with narrative text, mathematical equations, visualizations, interactive controls, and other extensive output. However, a number of challenges must be mastered in order to make existing workflows ready for interactive high-performance computing. With so many possibilities, it's easy to lose sight of the big picture. This course provides a detailed introduction to interactive high-performance computing.

    The following topics are covered:


    Opportunities and challenges of interactive HPC
    Functionality and interaction of the necessary components
    Introduction to the most important libraries
    Coupling and control of simulations
    Visualizing results interactively


     

    Prerequisites: Experience in Python

    Application
    Registrations are only considered until 15 March 2018 due to available space, the maximal number of participants is limited. Applicants will be notified, whether they are accepted for participitation.

    Instructors: Jens Henrik Göbbert, Alice Grosch, JSC

    Contact
    For any questions concerning the course please send an e-mail to j.goebbert@fz-juelich.de
    events.prace-ri.eu/event/826/
    Apr 9 9:00 to Apr 10 16:30
    The registration to this course is now open.

    All PATC Courses at BSC do not charge fees.

    PLEASE BRING YOUR OWN LAPTOP.

    Local Web Page: This course will provide very good introduction to the PUMPS Summer School run jointly with NVIDIA -also  at Campus Nord, Barcelona. For further information visit the school website  as this school has attendee selection process.
    You may also be interested in our Introduction to OpenACC course.

    Convener: 
    Antonio Peña, Computer Sciences Senior Researcher, Accelerators and Communications for High Performance Computing, BSC

    Objectives: 

    The aim of this course is to provide students with knowledge and hands-on experience in developing applications software for processors with massively parallel computing resources. In general, we refer to a processor as massively parallel if it has the ability to complete more than 64 arithmetic operations per clock cycle. Many commercial offerings from NVIDIA, AMD, and Intel already offer such levels of concurrency. Effectively programming these processors will require in-depth knowledge about parallel programming principles, as well as the parallelism models, communication models, and resource limitations of these processors.

    Agenda:

    DAY 1

    Session 1 / 9:00am – 1:00 pm (3:30 h lectures)

    L1 9:00-10:45 The GPU hardware: Many-core Nvidia developments

    10:45-11:15 Coffee break

    L2 11:15-13:00 CUDA Programming: Threads, blocks, kernels, grids

    13:00-14:00 Lunch break

     

    Session 2 / 2:00pm – 6:00 pm (3:30 h lectures)

    L3 14:00-15:45 CUDA Tools: Compiling, debugging, profiling, occupancy calculator

    15:45-16:15 Coffee break

    L4 16:15-18:00 CUDA Examples(1): VectorAdd, Stencil, ReverseArray

     

    DAY 2

    Session 3 / 9:00am – 1:00 pm (3:30 h lectures)

    L5   9:00-10:45 CUDA Examples (2): Matrices Multiply. Assorted optimizations

    10:45-11:15 Coffee break

    L6 11:15-13:00 CUDA Examples (3): Dynamic parallelism, Hyper-Q, unified memory

    13:00-14:00 Lunch break

     

    Session 4 / 2:00pm – 6:00 pm (3:30 h practical)

    H1 14:00-15:45 Hands-on Lab 1

    15:45-16:15 Coffee break

    H2 16:15-18:00 Hands-on Lab 2

     

    DAY 3

    Session 5 / 9:00am – 1:00 pm (3:30 h lectures)

    L7 9:00-10:45 Inside Pascal: Multiprocessors, stacked memory, NV-link

    10:45-11:15 Coffee break

    L8 11:15-13:00 OpenACC and other approaches to GPU computing

    13:00-14:00 Lunch break

     

    Session 6 / 2:00pm – 6:00 pm (3:30 h practical)

    H3 14:00-15:45 Hands-on Lab 3

    15:45-16:15 Coffee break

    H4 16:15-18:00 Hands-on Lab 4

     

    DAY 4

    Session 7 / 9:00am – 1:00 pm (3:30 h practical)

    H5 9:00-10:45 Hands-on Lab 5

    10:45-11:15 Coffee break

    H6 11:15-13:00 Hands-on Lab 6

    13:00-14:00 Lunch break

     

    Session 8 / 2:00pm – 6:00 pm (3:30 h practical)

    H7 14:00-15:45 Hands-on Lab 7

     15:45-16:15 Coffee break

    H8 16:15-18:00 Free Hands-on Lab

    End of Course

    The target audiences of the course are students who want to develop exciting applications for these processors, as well as those who want to develop programming tools and future implementations for these processors.

    Level: INTERMEDIATE: for trainees with some theoretical and practical knowledge; those who finished the beginners course

    ADVANCED: for trainees able to work independently and requiring guidance for solving complex problems

    Prerequisites: Basics of C programming and concepts of parallel processing will help, but are not critical to follow the lectures.
    events.prace-ri.eu/event/768/
    Apr 8 9:00 to Apr 11 18:00
    12
     
    13
     
    14
     
    15
     
    Meteorological and climate modelling

    16 April 2019

    Learning Outcome

    After the course the participants should be able to efficiently use WRF and other such applications for climate modelling or weather prediction. They should be able to customise the application configuration files based on their needs and tune the model for most efficient performance.

    Prerequisites

    The course addresses participants who are familiar with the C/C++/Fortran programming languages and have working experience with the Linux operating system and the use of the command line. Experience with parallel programming and background in Climate/Meteorological modelling is desirable.

    Bring your own laptop in order to be able to participate in the training hands on. Hands on work will be done in pairs so if you don’t have a laptop you might work with a colleague.

    Course language is English.

    Registration

    The maximum number of participants is 25.

    Registrations will be evaluated on a first-come, first-served basis. GRNET is responsible for the selection of the participants on the basis of the training requirements and the technical skills of the candidates. GRNET will also seek to guarantee the maximum possible geographical coverage with the participation of candidates from many countries.

    Venue

    GRNET headquarters

    Address: 2nd  Floor, 7, Kifisias Av. GR 115 23 Athens

    Information on how to reach GRNET headquarters ia available on GRNET website: grnet.gr/en/contact-us/  

    Accommodation options near GRNET can be found at: grnet.gr/wp-content/up.....n.pdf

    ARIS - System Information

    ARIS is the name of the Greek supercomputer, deployed and operated by GRNET (Greek Research and Technology Network) in Athens. ARIS consists of 532 computational nodes seperated in four “islands” as listed here:



    426 thin nodes: Regular compute nodes without accelerator.


    44 gpu nodes: “2 x NVIDIA Tesla k40m” accelerated nodes.


    18 phi nodes: “2 x INTEL Xeon Phi 7120p” accelerated nodes.


    44 fat nodes: Fat compute nodes have larger number of cores and memory per core than a thin node.



    All the nodes are connected via Infiniband network and share 2PB GPFS storage.The infrastructure also has an IBM TS3500 library of maximum storage capacity of about 6 PB. Access to the system is provided by two login nodes.

    About Tutors

    Dr. Dellis (Male) holds a B.Sc. in Chemistry (1990) and PhD in Computational Chemistry (1995) from the National and Kapodistrian University of Athens, Greece. He has extensive HPC and grid computing experience. He was using HPC systems in computational chemistry research projects on fz-juelich machines (2003-2005). He received an HPC-Europa grant on BSC (2009). In EGEE/EGI projects he acted as application support and VO software manager for SEE VO, grid sites administrator (HG-02, GR-06), NGI_GRNET support staff (2008-2014). In PRACE 1IP/2IP/3IP/4IP/5IP he was involved in benchmarking tasks either as group member or as BCO (2010-2017). Currently he holds the position of “Senior HPC Applications Support Engineer” at GRNET S.A. where he is responsible for activities related to user consultations, porting, optimization and running HPC applications at national and international resources.

    Dr. Theodore M. Giannaros (male), born in 1982, holds a PhD in Atmospheric Physics (Aristotle University of Thessaloniki, 2013). In 2014, he joined the National Observatory of Athens (NOA) where he currently acts as a post-doc researcher. His research interests and expertise include numerical modeling focusing primarily on severe weather, urban meteorology and climatology, focusing on the study of the urban heat island effect, human biometeorology, with emphasis on the evaluation of the thermal bioclimate, and regional climate modeling. He has published 22 papers in international peer-review scientific journals. His citation report includes 225 citations and an h-index of 8. Dr. Giannaros has worked extensively with the WRF and MM5 meteorological models, and the RayMan micro-scale model. He is experienced in several programming and scripting languages (Fortran, Python, GDAL, NCO, CDO, Bash), and he is proficient in using geographic information systems (ArcGIS, Quantum GIS).

    Stergios Kartsios was born in 1987 and received his B.Sc. in Physics and his M.Sc. in Meteorology and Climatology from the Aristotle University of Thessaloniki. He is a PhD candidate in the Department of Meteorology and Climatology where he works as a research assistant. He is using the Weather Research and Forecasting (WRF) model in a number of applications such, as an operational forecasting tool at his Department, as a regional climate model in the framework of EURO-CORDEX from mesoscale to convective permitting simulations and as a research tool for very high-resolution simulations over Greece. He evaluates model performance against multiple surface observations, radar and satellite data. He also uses the WRF-SFIRE model to investigate atmosphere-fire interactions. He has participated in three research programes and has 3 publications in peer-review journals. He has also working experience as junior forecaster in the private sector. Mr. Kartsios is experienced in a number of programming languages and shell scripting, while he was presenter and instractor in a number of whorkshops and conferences.

    Dr Aristeidis Sotiropoulos received his BSc in Computer Science in 1998 from the University of Crete, Greece and his PhD in Parallel Processing and Cluster Computing in 2004 from the National Technical University of Athens, Greece. His interests mainly focus on the fields of Large Scale Computing & Storage Systems, System Software for Scalable High Speed Interconnects for Computer Clusters and Advanced Microprocessor Architectures. He has published several scientific papers in international journals and conference proceedings. He has received the IEEE IPDPS 2001 best paper award for the paper "Minimizing Completion Time for Loop Tiling with Computation and Communication Overlapping". He has worked in several European and National R&D programs in the field of High Performance Computing, Grid Computing, Cloud Computing and Storage. In 2013, he was appointed as the Head of Operations and Financial Management Services, in charge of 15 people. Currently, he is managing EC projects at GRNET SA, the Greek NREN responsible for the provision of advanced e-infrastructure services to the Greek Academic and Research Community.

    About GRNET

    GRNET provides Internet connectivity, high-quality e-Infrastructures and advanced services to the Greek Educational, Academic and Research community.

    Through its high-speed, high-capacity infrastructure that spans across the entire country, GRNET interconnects more than 150 institutions, including all universities and technological institutions, as well as many research institutes and the public Greek School Network.

    GRNET operates the National High Performance Computing system (a Tier-1 in the European HPC ecosystem) and offers user and application support services, that provide Greek scientists with the computing infrastructure and expertise they need for their research enabling them to perform large scale simulations.

    GRNET offers innovative IaaS cloud computing services to the Greek and global research & education communities: “ ~okeanos” and “okeanos global” allow users to create multi-layer virtual infrastructure and instantiate virtual computing machines, local networks to interconnect them, and a reliable storage space within seconds, with few, simple mouse clicks.

    GRNET aims at contributing towards Greece’s Digital Convergence with the EU, by supporting the development and encouraging the use of e-Infrastructures and services. The right and timely planning strategies, together with the long experience and know-how of its people, guarantee the continuation and enhancement of GRNET’s successful course.

    Greek Research and Technology Network – Networking Reserach and Education:

    www.grnet.gr, hpc.grnet.gr
    events.prace-ri.eu/event/797/
    Apr 16 9:30 16:30
    Since the 2011 revision to the C++ language and standard library, the ways it is now being used are quite different. Used well, these features enable the programmer to write elegant, reusable and portable code that runs efficiently on a variety of architectures.


    However it is still a very large and complex tool. This course will cover a minimal set of features to allow an experienced non-C++ programmer to get to grips with language. These include: overloading, templates, containers, iterators, lambdas and standard algorithms. It concludes with a brief discussion of modern frameworks for portable parallel performance which are commonly implemented in C++.


    The course would appeal to existing C++ programmers wanting to learn techniques that are applicable to numerical computing, or C programmers who want to know what parts of the C++ standard they should prioritise when learning new features.

    Course materials

    Timetable

    Details to follow

    Tuesday

    9:00 - 10:00  Welcome and setup

    10:00 - 17:00 Day 1

    Wednesday

    9:00 - 16:00 Day 2
    events.prace-ri.eu/event/853/
    Apr 16 10:00 to Apr 17 18:30
    Since the 2011 revision to the C++ language and standard library, the ways it is now being used are quite different. Used well, these features enable the programmer to write elegant, reusable and portable code that runs efficiently on a variety of architectures.


    However it is still a very large and complex tool. This course will cover a minimal set of features to allow an experienced non-C++ programmer to get to grips with language. These include: overloading, templates, containers, iterators, lambdas and standard algorithms. It concludes with a brief discussion of modern frameworks for portable parallel performance which are commonly implemented in C++.


    The course would appeal to existing C++ programmers wanting to learn techniques that are applicable to numerical computing, or C programmers who want to know what parts of the C++ standard they should prioritise when learning new features.

    Course materials

    Timetable

    Details to follow

    Tuesday

    9:00 - 10:00  Welcome and setup

    10:00 - 17:00 Day 1

    Wednesday

    9:00 - 16:00 Day 2
    events.prace-ri.eu/event/853/
    Apr 16 10:00 to Apr 17 18:30
    18
     
    19
     
    20
     
    21
     
    22
     
    23
     
    Annotation

    The R part of course (first day) will be focused on presenting the basics of data analysis in R and visualization of data. The course will cover the introduction to the R statistical language introducing the basic data types and workflow. Afterwards, packages from the “tidyverse” collection will be presented. These includes packages for the loading of data, preprocessing data, basic data exploration, and visualization.

    The Python oriented part (second day) will introduce essential data-scientific packages and will be complemented with hands-on exercises that will demonstrate their usage with real world data analytic problems, and showing how to tackle such problems.

    The course will be up to 50% hands-on exercises covering all topics to practice the techniques, and patterns gained.

    Purpose of the course (benefits for the attendees)

    Target audience: Users that want to use Python and/or R for data analysis and prototyping. The participants will learn basic and intermediate skills for exploratory data analysis and visualization in the programming languages of R and Python.

    About the tutor(s)

    Tomáš Martinovič obtained his PhD in computational sciences at IT4Innovations, VSB - Technical University of Ostrava in 2018. From 2015 to 2018 he worked in a team focused on analysis of complex dynamical systems, where he worked on scalable implementations of algorithms from the field of nonlinear time series analysis. Since the start of 2019 he has been working in a team focused on high performance data analysis with the defined objective of research and transfer of knowledge in cooperation with industry.

    Stanislav Böhm has a PhD in computer science, and is a researcher at IT4Innovations. He is interested in distributed systems, verification, and scheduling.
    events.prace-ri.eu/event/869/
    Apr 24 9:30 to Apr 25 15:30
    32nd VI-HPS Tuning Workshop (Bristol, England) - PATC course

    Date

    Wednesday 24th - Friday 26th April 2019

    Location

    The workshop will take place at the University of Bristol, England.

    Co-organizing Institutions



    Goals

    This workshop is organised by VI-HPS for the UK PRACE Advanced Training Centre to:


    give an overview of the VI-HPS programming tools suite
    explain the functionality of individual tools, and how to use them effectively
    offer hands-on experience and expert assistance using the tools


    On completion participants should be familiar with common performance analysis and diagnosis techniques and how they can be employed in practice (on a range of HPC systems). Those who prepared their own application test cases will have been coached in the tuning of their measurement and analysis, and provided optimization suggestions.

    Programme Overview

    Presentations and hands-on sessions are on the following topics:


    BSC tools for trace analysis and performance prediction
    Score-P instrumentation and measurement
    Scalasca automated trace analysis
    TAU performance system


    A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

    The workshop will be held in English and run from 09:00 to not later than 17:00 each day, with breaks for lunch and refreshments. There is no fee for participation, however, participants are responsible for their own travel and accommodation.

    Classroom capacity is limited, therefore priority will be given to applicants with MPI, OpenMP and hybrid OpenMP+MPI parallel codes already running on the workshop computer systems, and those bringing codes from similar systems to work on. Attendees will need to bring their own notebook computers (with SSH and X11 configured) and use (eduroam) wifi to connect to the workshop computer systems.

    Outline

    The workshop introduces tools that provide a practical basis for portable performance analysis of parallel application execution, covering both profiling and tracing. It will be delivered as a series of presentations with associated hands-on practical exercises using the ARM-based Isambard Cray XC50 computer.

    While analysis of provided example codes will be used to guide the class through the relevant steps and familiarise with usage of the tools, coaching will also be available to assist participants to analyse their own parallel application codes and may suggest opportunities for improving their execution performance and scalability.

    Programme (preliminary)




    Day 1:
    Wednesday 24th April


    09:30
    Welcome messages

    ARCHER Training Courses




    09:45
    Introduction

    Introduction to VI-HPS & overview of tools
    Introduction to parallel performance engineering
    Computer systems and software environment




    11:00
    (break)


    11:30
    Cray tools




    13:00
    (lunch)


    14:00
    BSC performance tools


    15:00
    (break)


    15:30
    Hands-on coaching to apply tools to analyze participants' own code(s).


    17:15
    Review of day and schedule for remainder of workshop


    17:30
    (adjourn)


     


    Day 2:
    Thursday 25th April


    09:30
    Instrumentation & measurement with Score-P
    Execution profile analysis report exploration with CUBE


    11:00
    (break)


    11:30
    TAU performance system


    13:00
    (lunch)


    14:00
    Hands-on coaching to apply tools to analyze participants' own code(s).


    17:30
    (adjourn)


     


    Day 3:
    Friday 26th April


    09:30
    Automated trace analysis with Scalasca


    11:00
    (break)


    11:30
    TAU PerfExplorer


    13:00
    (lunch)


    14:00
    Hands-on coaching to apply tools to analyze participants' own code(s).


    16:45
    Review of workshop


    17:00
    (adjourn)




    Hardware and Software Platforms

    Isambard: Cray XC50 with 164 dual Marvell ThunderX2 32-core 2.1 GHz nodes (64-bit ARMv8-A cores) with 256GB DRAM and Aries dragonfly interconnect, Cray MPI, Cray, GCC & ARM toolchains. Training accounts will be provided!

    ARCHER: Cray XC30 with 3008 compute nodes consisting of two 12-core Intel E5-2697 (IvyBridge) processors sharing 64GB (or 128GB) of NUMA memory, Aries dragonfly interconnect, Cray MPI, Cray, GCC & Intel compilers, PBS Pro job management system. Training accounts will be provided!

    Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited. Participants are expected to already possess user accounts on non-local systems they intend to use, and should be familiar with the procedures for compiling and running parallel applications.

    Registration

    Please register via the Registration tab on this page.

    Local organisers information page.
    events.prace-ri.eu/event/867/
    Apr 24 10:00 to Apr 26 18:30
    Annotation

    The R part of course (first day) will be focused on presenting the basics of data analysis in R and visualization of data. The course will cover the introduction to the R statistical language introducing the basic data types and workflow. Afterwards, packages from the “tidyverse” collection will be presented. These includes packages for the loading of data, preprocessing data, basic data exploration, and visualization.

    The Python oriented part (second day) will introduce essential data-scientific packages and will be complemented with hands-on exercises that will demonstrate their usage with real world data analytic problems, and showing how to tackle such problems.

    The course will be up to 50% hands-on exercises covering all topics to practice the techniques, and patterns gained.

    Purpose of the course (benefits for the attendees)

    Target audience: Users that want to use Python and/or R for data analysis and prototyping. The participants will learn basic and intermediate skills for exploratory data analysis and visualization in the programming languages of R and Python.

    About the tutor(s)

    Tomáš Martinovič obtained his PhD in computational sciences at IT4Innovations, VSB - Technical University of Ostrava in 2018. From 2015 to 2018 he worked in a team focused on analysis of complex dynamical systems, where he worked on scalable implementations of algorithms from the field of nonlinear time series analysis. Since the start of 2019 he has been working in a team focused on high performance data analysis with the defined objective of research and transfer of knowledge in cooperation with industry.

    Stanislav Böhm has a PhD in computer science, and is a researcher at IT4Innovations. He is interested in distributed systems, verification, and scheduling.
    events.prace-ri.eu/event/869/
    Apr 24 9:30 to Apr 25 15:30
    32nd VI-HPS Tuning Workshop (Bristol, England) - PATC course

    Date

    Wednesday 24th - Friday 26th April 2019

    Location

    The workshop will take place at the University of Bristol, England.

    Co-organizing Institutions



    Goals

    This workshop is organised by VI-HPS for the UK PRACE Advanced Training Centre to:


    give an overview of the VI-HPS programming tools suite
    explain the functionality of individual tools, and how to use them effectively
    offer hands-on experience and expert assistance using the tools


    On completion participants should be familiar with common performance analysis and diagnosis techniques and how they can be employed in practice (on a range of HPC systems). Those who prepared their own application test cases will have been coached in the tuning of their measurement and analysis, and provided optimization suggestions.

    Programme Overview

    Presentations and hands-on sessions are on the following topics:


    BSC tools for trace analysis and performance prediction
    Score-P instrumentation and measurement
    Scalasca automated trace analysis
    TAU performance system


    A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

    The workshop will be held in English and run from 09:00 to not later than 17:00 each day, with breaks for lunch and refreshments. There is no fee for participation, however, participants are responsible for their own travel and accommodation.

    Classroom capacity is limited, therefore priority will be given to applicants with MPI, OpenMP and hybrid OpenMP+MPI parallel codes already running on the workshop computer systems, and those bringing codes from similar systems to work on. Attendees will need to bring their own notebook computers (with SSH and X11 configured) and use (eduroam) wifi to connect to the workshop computer systems.

    Outline

    The workshop introduces tools that provide a practical basis for portable performance analysis of parallel application execution, covering both profiling and tracing. It will be delivered as a series of presentations with associated hands-on practical exercises using the ARM-based Isambard Cray XC50 computer.

    While analysis of provided example codes will be used to guide the class through the relevant steps and familiarise with usage of the tools, coaching will also be available to assist participants to analyse their own parallel application codes and may suggest opportunities for improving their execution performance and scalability.

    Programme (preliminary)




    Day 1:
    Wednesday 24th April


    09:30
    Welcome messages

    ARCHER Training Courses




    09:45
    Introduction

    Introduction to VI-HPS & overview of tools
    Introduction to parallel performance engineering
    Computer systems and software environment




    11:00
    (break)


    11:30
    Cray tools




    13:00
    (lunch)


    14:00
    BSC performance tools


    15:00
    (break)


    15:30
    Hands-on coaching to apply tools to analyze participants' own code(s).


    17:15
    Review of day and schedule for remainder of workshop


    17:30
    (adjourn)


     


    Day 2:
    Thursday 25th April


    09:30
    Instrumentation & measurement with Score-P
    Execution profile analysis report exploration with CUBE


    11:00
    (break)


    11:30
    TAU performance system


    13:00
    (lunch)


    14:00
    Hands-on coaching to apply tools to analyze participants' own code(s).


    17:30
    (adjourn)


     


    Day 3:
    Friday 26th April


    09:30
    Automated trace analysis with Scalasca


    11:00
    (break)


    11:30
    TAU PerfExplorer


    13:00
    (lunch)


    14:00
    Hands-on coaching to apply tools to analyze participants' own code(s).


    16:45
    Review of workshop


    17:00
    (adjourn)




    Hardware and Software Platforms

    Isambard: Cray XC50 with 164 dual Marvell ThunderX2 32-core 2.1 GHz nodes (64-bit ARMv8-A cores) with 256GB DRAM and Aries dragonfly interconnect, Cray MPI, Cray, GCC & ARM toolchains. Training accounts will be provided!

    ARCHER: Cray XC30 with 3008 compute nodes consisting of two 12-core Intel E5-2697 (IvyBridge) processors sharing 64GB (or 128GB) of NUMA memory, Aries dragonfly interconnect, Cray MPI, Cray, GCC & Intel compilers, PBS Pro job management system. Training accounts will be provided!

    Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited. Participants are expected to already possess user accounts on non-local systems they intend to use, and should be familiar with the procedures for compiling and running parallel applications.

    Registration

    Please register via the Registration tab on this page.

    Local organisers information page.
    events.prace-ri.eu/event/867/
    Apr 24 10:00 to Apr 26 18:30
    32nd VI-HPS Tuning Workshop (Bristol, England) - PATC course

    Date

    Wednesday 24th - Friday 26th April 2019

    Location

    The workshop will take place at the University of Bristol, England.

    Co-organizing Institutions



    Goals

    This workshop is organised by VI-HPS for the UK PRACE Advanced Training Centre to:


    give an overview of the VI-HPS programming tools suite
    explain the functionality of individual tools, and how to use them effectively
    offer hands-on experience and expert assistance using the tools


    On completion participants should be familiar with common performance analysis and diagnosis techniques and how they can be employed in practice (on a range of HPC systems). Those who prepared their own application test cases will have been coached in the tuning of their measurement and analysis, and provided optimization suggestions.

    Programme Overview

    Presentations and hands-on sessions are on the following topics:


    BSC tools for trace analysis and performance prediction
    Score-P instrumentation and measurement
    Scalasca automated trace analysis
    TAU performance system


    A brief overview of the capabilities of these and associated tools is provided in the VI-HPS Tools Guide.

    The workshop will be held in English and run from 09:00 to not later than 17:00 each day, with breaks for lunch and refreshments. There is no fee for participation, however, participants are responsible for their own travel and accommodation.

    Classroom capacity is limited, therefore priority will be given to applicants with MPI, OpenMP and hybrid OpenMP+MPI parallel codes already running on the workshop computer systems, and those bringing codes from similar systems to work on. Attendees will need to bring their own notebook computers (with SSH and X11 configured) and use (eduroam) wifi to connect to the workshop computer systems.

    Outline

    The workshop introduces tools that provide a practical basis for portable performance analysis of parallel application execution, covering both profiling and tracing. It will be delivered as a series of presentations with associated hands-on practical exercises using the ARM-based Isambard Cray XC50 computer.

    While analysis of provided example codes will be used to guide the class through the relevant steps and familiarise with usage of the tools, coaching will also be available to assist participants to analyse their own parallel application codes and may suggest opportunities for improving their execution performance and scalability.

    Programme (preliminary)




    Day 1:
    Wednesday 24th April


    09:30
    Welcome messages

    ARCHER Training Courses




    09:45
    Introduction

    Introduction to VI-HPS & overview of tools
    Introduction to parallel performance engineering
    Computer systems and software environment




    11:00
    (break)


    11:30
    Cray tools




    13:00
    (lunch)


    14:00
    BSC performance tools


    15:00
    (break)


    15:30
    Hands-on coaching to apply tools to analyze participants' own code(s).


    17:15
    Review of day and schedule for remainder of workshop


    17:30
    (adjourn)


     


    Day 2:
    Thursday 25th April


    09:30
    Instrumentation & measurement with Score-P
    Execution profile analysis report exploration with CUBE


    11:00
    (break)


    11:30
    TAU performance system


    13:00
    (lunch)


    14:00
    Hands-on coaching to apply tools to analyze participants' own code(s).


    17:30
    (adjourn)


     


    Day 3:
    Friday 26th April


    09:30
    Automated trace analysis with Scalasca


    11:00
    (break)


    11:30
    TAU PerfExplorer


    13:00
    (lunch)


    14:00
    Hands-on coaching to apply tools to analyze participants' own code(s).


    16:45
    Review of workshop


    17:00
    (adjourn)




    Hardware and Software Platforms

    Isambard: Cray XC50 with 164 dual Marvell ThunderX2 32-core 2.1 GHz nodes (64-bit ARMv8-A cores) with 256GB DRAM and Aries dragonfly interconnect, Cray MPI, Cray, GCC & ARM toolchains. Training accounts will be provided!

    ARCHER: Cray XC30 with 3008 compute nodes consisting of two 12-core Intel E5-2697 (IvyBridge) processors sharing 64GB (or 128GB) of NUMA memory, Aries dragonfly interconnect, Cray MPI, Cray, GCC & Intel compilers, PBS Pro job management system. Training accounts will be provided!

    Other systems where up-to-date versions of the tools are installed can also be used when preferred, though support may be limited. Participants are expected to already possess user accounts on non-local systems they intend to use, and should be familiar with the procedures for compiling and running parallel applications.

    Registration

    Please register via the Registration tab on this page.

    Local organisers information page.
    events.prace-ri.eu/event/867/
    Apr 24 10:00 to Apr 26 18:30
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